Reduction of power consumption and the increase of high speed data operation are the major targets for the next generation logic circuit. Drastic increase of static power dissipation is being anticipated due to leakage current in nanometer-scaled CMOS technology. In addition, increase in the length of global interconnection in advanced VLSIs results in further increase of both power and delay. Logic-in memory architecture, where memory elements are distributed over a logic-circuit plane, combined with nonvolatile memory is expected to realize both ultra-low power and shorten interconnection delay. However, in order to fully take advantage of the logic-in-memory architecture, it is important to implement a nonvolatile memory that has a capability of shorter access time, unlimited endurance, scalable write, and small dimension comparable to the employed CMOS technology.
As a result there is a surge of innovative development in low power devices and design techniques. In most cases, the requirements for low power consumption must meet the equally demanding goals of high chip density and high throughput circuits. Hence, low power digital design and digital ICs are very active fields of research and development. These fields have contributed to the rise of power as a major design parameter on par with performance and die size. In fact, power consumption is regarded as the limiting factor in the continuing scaling of CMOS technology. To respond to this challenge, a memory technology that combines higher density with non-volatility and reduced power consumption in a cost-effective manner can prove desirable and provide a basis for a wide range of data applications.
Embedded SRAMs is one of the most frequently used memory embedded in logic chips, and typical applications include on-chips buffers, caches, register files, and so on. The small access time makes it popular in the logic ICs industry. Nonetheless, its volatility and the need of an external nonvolatile memory to store the configuration data make it not suitable for nowadays embedded applications. Indeed, in embedded FPGA devices, the use of a nonvolatile internal memory like flash technology allows the chip to be powered down in the standby mode when not in use in order to reduce power consumption. Indeed, these FPGAs use flash memory in there configuration layer which makes it ready to run at power up. However, distribution of the memory all over the chip raises some technological constraints and needs additional masks (10 to 15 for flash technology) and dedicated process steps thereby increasing the chip cost. Moreover, these FPGAs are not fast reprogramming speed due to the high-access time inherent to the flash memory.
There are a number of conventional methods for decreasing power consumption. These include “clock gating,” in which the circuit clock is stopped when arithmetic processing is not being performed, and “power gating,” in which power is shut down to circuits not performing operational processing. However, with clock gating, it is not possible to stop leakage current in the circuit, reducing the power-saving effects, and with power gating, although most of the leakage current can be stopped by shutting off power, it cannot be completely eliminated due to the need for power to be supplied to the register. In contrast, with nonvolatile logic technology power can but shut off to the circuit, including for the register, making it possible to reduce power consumption to zero.
An alternative is to adjust the SRAM cells to integrate a nonvolatile (nv) component. Several nv-SRAM technologies have been proposed integration non-volatile components (type flash) to the SRAM cell. But the more mature and more reliable architecture use no less than 12 transistors per cell, which has a strong impact on the density and cost. Furthermore, writing/erasing voltages of Flash are high and not very compatible with supply voltages of SRAM cells, which impose additional devices. Finally, these technologies have a low endurance (<1E10) and they are poorly suited for applications such as cache memory (embedded memory in logic ICs devices) and can ensure a fair backup at very low frequencies.
The use of nonvolatile memories such as MRAMs helps to overcome the drawbacks of classical SRAM-based logic ICs without significant speed penalty. Besides its advantage that lies in power saving during the standby mode, it also benefits to the configuration time reduction since there is no need to load the configuration data from an external nonvolatile memory as used in SRAM based logic ICs. Furthermore, during the circuit operation, the MRAM devices can be written which allows a dynamic (or shadowed) configuration and further increases the flexibility of Logic ICs circuit based on the MRAM. On the other hand, MRAM memories have shown interesting features that include high-timing performance, high-density integration, reliable data storage, good endurance, and low number of additional masks for the magnetic postprocess (The integration of MRAM devices is made by an “above-CMOS” technology (the magnetic back-end process can be done after the CMOS front-end process)).
Non-volatile registers are a data storage circuits which retain stored information in the absence of power. In digital processing (logic) circuits the storage area used to temporarily retain mid-calculation data, arithmetic processing, or operational status is called a register. Generally, registers are dispersed within the logic circuit. Logic ICs (i.e. CPUs) and Field Programmable Gate array (FPGA), contain this kind of registers, which temporarily retain the status of various processes, background information, and the operational status of other ICs and peripheral equipment. Conventional logic ICs are volatile, meaning shutting off power to the IC will cause information in the register to be lost. Therefore, power must constantly be supplied to the IC.
Turning now to FIG. 1, a simplified block diagram of an n-bit serial-in-parallel-out (SIPO) register 10 is illustrated. Register include a plurality of register cells 1, each of which has input D, a clock input CK, data output Q and inverse data QN.
These are the simplest kind of shift register. The data string is presented at ‘Data In’, and is shifted right one stage each time ‘Data Advance’ (clock signal) is brought high. At each advance, the bit on the far left (i.e. ‘Data In’) is shifted into the first flip-flop's output. The bit on the far right (i.e. ‘Data Out’) is shifted out for a read operation and can be lost. As a data string is clocked to the register, any bytes or word stored in the register is simultaneously read in parallel at data outputs Qi. As understood by those skilled in the art, these kinds of registers are most commonly used as a serial distributed memory or a bit stream.